1. Field of the Invention
The present invention relates to, for example, a video signal processing apparatus, a video signal processing method, a computer program product, and an image display apparatus which are suitable to be applied for displaying a wipe image on a display screen. In detail, this invention relates to a video signal processing apparatus, etc., in which a synthesized video signal is generated by taking out main area parts contributing to an actual image display as well as border area parts from first and second video signals, and an output video signal is obtained by removing the border area parts after a predetermined image processing is performed on the synthesized video signal so that no gap is generated between a switching position for images and also the images at the switching position are displayed as the identical images on a full screen.
2. Description of the Related Art
Up to now, as an image display apparatus, for example, an image display apparatus having a wipe function is known as described in Japanese Unexamined Patent Application Publication No. 1-251185, etc. FIG. 11 illustrates a wipe operation example. An image A is displayed based on a first video signal, and an image B is displayed based on a second video signal. With respect to a wipe position (border position) horizontally dividing the screen, the image A is displayed before the wipe position, and the image B is displayed after the wipe position. As the wipe position is shifted from the left to the right, a display area for the image A is larger, and a display area for the image B is smaller.
During the wipe operation, an image based on a synthesized video signal is displayed in which the first video signal and the second video signal are synthesized. At this time, when a signal at a line N of the synthesized video signal is focused on, the signal at the line N is switched from the first video signal to the second video signal at the wipe position functioning as a border.
The wipe function is used for a special effect when the first image signal is transited to the second image signal, and also used when a difference between the two image based on the first and second image signals is observed. For example, an image based on a first video signal subjected to compression/decompression according to a first compression method and an image based on a second video signal subjected to compression/decompression according to a second compression method are displayed on the same screen. A difference in each part is observed by changing the wipe position to assess performances of the first and second compression methods and then compression parameters are accordingly adjusted, for example. When the difference between the two images based on the first and second image signals is observed in this way, such a situation is avoided that a gap at the switching position between the two images is generated.
FIG. 12 illustrates an example of an image display apparatus 200 having a wipe operation function in the related art. The image display apparatus 200 is provided with a selector 201, an IP conversion circuit 202, a high frequency compensation circuit 203, and an LCD (Liquid Crystal Display) 204.
A first video signal Sa and a second video signal Sb are input to the selector 201 while the first video signal Sa and the second video signal Sb are mutually synchronized. The video signals Sa and Sb are both interlace signals. Also, the selector 201 is supplied with a wipe switching control signal WS. The wipe switching control signal WS is in one state before a wipe position (border position) WP horizontally dividing the screen, for example, “0”, and is in the other state, for example, “1”.
The selector 201 is adapted to selectively take out the video signal Sa or the video signal Sb based on the wipe switching control signal WS to the synthesized video signal. That is, the selector 201 takes out the video signal Sa when the wipe switching control signal WS is in the one state, and takes out the video signal Sb when the wipe switching control signal WS is in the other state.
The IP conversion circuit 202 is adapted to convert the synthesized video signal obtained in the selector 201 from an interlace signal to a progressive signal. FIG. 13 illustrates a configuration example of the IP conversion circuit 202. The IP conversion circuit 202 is composed of an interpolation signal generation circuit 221, an N field memory 222, a motion determination circuit 223, and an interpolation pixel selection circuit 224.
The interlace signals Sint are input to the interpolation signal generation circuit 221. The interpolation signal generation circuit 221 is adapted to generate interpolation signals for the motion picture (interpolation line signals) from signals in the current field. The interpolation signal generation circuit 221 generates signals for the respective interpolation pixels constituting the interpolation line signals through a diagonal interpolation or a vertical interpolation. In a diagonal interpolation processing, pixel information in the vicinity of the interpolation pixels is used to detect a correlation in a diagonal direction. When it is determined that a correlation at a certain angle exists, signals at the upper and lower pixels in the diagonal direction are averaged to generate interpolation pixel signals. Also, in a vertical interpolation processing, signals at the upper and lower pixels with respect to the interpolation pixels are averaged to generate interpolation pixel signals.
The interlace signals Sint are input to the N field memory 222. The N field memory 222 stores and holds signals in N fields before the current field.
The interlace signals Sint (current field signals) and also signals in the past fields are input to the motion determination circuit 223 from the N field memory 222. The motion determination circuit 223 is adapted to determine whether this display is a motion picture or a still image in units of pixel by using the current field signals and the past field signals.
The interpolation pixel selection circuit 224 is adapted to generate and output the progressive signals Sprg based on signals in a field one before the field where the interlace signals Sint (current field signals) is output from the N field memory 222 and the interpolation line signal generated in the interpolation signal generation circuit 221. In this case, among the progressive signals Sprg, as signals in lines corresponding to the respective lines of the interlace signals Sint (current field signals), the interpolation pixel selection circuit 224 outputs the signals in the respective lines of the interlace signals Sint as they are. Also, as the interpolation line signals, when it is determined that this display is the motion picture in the motion determination circuit 223, the interpolation pixel selection circuit 224 outputs the signals generated in the interpolation signal generation circuit 221. When it is determined that this display is the still image in the motion determination circuit 223, the interpolation pixel selection circuit 224 outputs the signals in the field one before the current field.
FIGS. 14A to 14C illustrate examples of the interlace signals Sint, progressive signals Sprg through a diagonal interpolation, and progressive signals Sprg through a vertical interpolation. FIG. 14B illustrates the progressive signals Sprg obtained by subjecting the interlace signals Sint illustrated in FIG. 14A to the diagonal interpolation to generate interpolation signals. Through the diagonal interpolation, when it is determined that the correlation exists in the diagonal direction at the certain angle as described above, the signals at the upper and lower pixels in the diagonal direction are averaged to generate interpolation pixel signals, and therefore the diagonal line is smoothly interpolated.
In contrast to this, FIG. 14C illustrates the progressive signals Sprg obtained by subjecting the interlace signals Sint illustrated in FIG. 14A to the vertical interpolation to generate interpolation signals. Through the vertical interpolation, the signals at the upper and lower pixels with respect to the interpolation pixels are averaged to generate the interpolation pixel signals as described above, and therefore the diagonal line becomes blurring stepwise. For this phenomenon, the interpolation based on the diagonal interpolation is carried out in a large number of fixed pixel display apparatuses.
FIGS. 15A to 15C illustrate a motion determination in the motion determination circuit 223 (in the case of motion picture determination) and examples of the progressive signals Sprg generated in that case. The motion determination circuit 223 determines that this display is the motion picture because, for example, the signals in an N field (current field) are not the same as those in an N−2 field as illustrated in FIG. 15A. In this case, interpolation signals for the progressive signals Sprg are generated by using the signals in the N field (current field). FIG. 15B illustrates the progressive signals Sprg in a case where interpolation signals are generated through the diagonal interpolation. FIG. 15C illustrates the progressive signals Sprg in a case where interpolation signals are generated through the vertical interpolation.
FIGS. 16A and 16B illustrate a motion determination in the motion determination circuit 223 (in the case of still image determination) and examples of the progressive signals Sprg generated in that case. The motion determination circuit 223 determines that this display the still image because, for example, the signals in the N field (current field) are the same as those in the N−2 field as illustrated in FIG. 16A. In this case, as the interpolation signals for the progressive signals Sprg, signals in an N−1 field are used as they are. FIG. 16B illustrates the progressive signals Sprg when it is determined that this display the still image.
While returning back to FIG. 12, the high frequency compensation circuit 203 is adapted to emphasize high frequency components of the synthesized video signal (progressive signal) output from the IP conversion circuit 202. FIG. 17 illustrates a configuration example of the high frequency compensation circuit 203. The high frequency compensation circuit 203 is provided with a vertical high pass filter (vertical HPF) 231, a gain adjustment section 232, a horizontal high pass filter (horizontal HPF) 233, a gain adjustment section 234, and an adder 235.
The vertical HPF 231 is adapted to extract the high frequency components in the vertical direction from an input signal Sin. FIG. 18 illustrates a frequency characteristic example of the vertical HPF 231. In FIG. 18, a horizontal axis represents a space frequency, and a vertical axis represents an amplitude. Fs represents a sampling frequency in the vertical direction. The gain adjustment section 232 is adapted to adjust a gain of the high frequency components in the vertical direction extracted in the vertical HPF 231. Also, the horizontal HPF 233 is adapted to extract the high frequency components in the horizontal direction from the input signal Sin. A frequency characteristic of the horizontal HPF 233 is similar to the frequency characteristic illustrated in, for example, FIG. 18. It should be noted in this case that Fs represents a sampling frequency in the horizontal direction. The gain adjustment section 234 is adapted to adjust a gain of the high frequency components in the horizontal direction extracted in the horizontal HPF 233. The adder 235 is adapted to add the input signal Sin with the high frequency components in the vertical direction whose gain has been adjusted in the gain adjustment section 232 and the high frequency components in the horizontal direction whose gain has been adjusted in the gain adjustment section 234 to output an output signal Sout whose high component has been emphasized.
While returning back to FIG. 12, the LCD 204 constitutes a fixed pixel display element. The LCD 204 is adapted to an image based on the synthesized video signal output from the high frequency compensation circuit 203. It should be noted that a fixed pixel display element such as a PDP (Plasma Display Panel) can also be used instead of the LCD 204.
A description will be given of the wipe operation among operations in the image display apparatus 200 illustrated in FIG. 12.
The first video signal Sa which is an interlace signal and the second video signal Sb which is an interlace signal and synchronized with the first video signal Sa are supplied to the selector 201. FIG. 19A illustrates an image displayed on a screen based on the first video signal Sa (input image A), and FIG. 19B illustrates an image displayed on the screen based on the second video signal Sb (input image B).
In addition, the selector 201 is supplied with the wipe switching control signal WS. The wipe switching control signal WS is, as illustrated in FIG. 19C, in one state before the wipe position WP, for example, “0”. The wipe switching control signal WS is in the other state after the wipe position WP, for example, “1”. In the selector 201, when the wipe switching control signal WS is in the one state, the video signal Sa is taken out and on the other hand, when the wipe switching control signal WS is in the other state, the video signal Sb is taken out. In other words, the synthesized video signal in which the video signals Sa and Sb are switched while corresponding to the wipe position WP is output from the selector 201. FIG. 19D illustrates an image displayed on the screen based on the synthesized video signal (synthesized image).
The synthesized video signal (interlace signal) output from the selector 201 is supplied to the IP conversion circuit 202 and converted from the interlace signal to the progressive signal. Also, the synthesized video signal (progressive signal) output from the IP conversion circuit 202 is supplied to the high frequency compensation circuit 203, and the high frequency components are emphasized. Then, the synthesized video signal output from the high frequency compensation circuit 203 is supplied to the LCD 204. FIG. 19E illustrates an image displayed on the screen of the LCD 204 (output image). That is, on the screen of the LCD 204, the image based on the first video signal Sa is displayed before the wipe position WP, and the image based on the second video signal Sb is displayed after the wipe position WP. When the wipe position WP is shifted from the left to the right, in other words, when the change position from “0” to “1” of the wipe switching control signal WS is delayed, the display area for the image based on the first video signal Sa is larger, and the display area for the image based on the second video signal Sb is smaller.